The main power supply for the internal NAND flash memory core. It typically operates at 2.97V to 3.3V .
While exact pad positions can vary slightly based on specific manufacturer layouts (e.g., Samsung, SK Hynix, Micron), JEDEC sets standardized assignment zones. Below is a functional layout summary of critical pins found in a typical UFS BGA 153 package. Pad Coordinate Signal Name Description NAND Flash Core Power Rail (2.5V - 3.3V) C3, C4 M-PHY Interface Power Rail (1.2V) E3, E4 Logic/Controller Power Rail (1.2V) B2 Hardware Reset (Active Low) D2 Reference Clock Input F1 Lane 0 Receive Data (True) F2 Lane 0 Receive Data (Complement) G1 Lane 0 Transmit Data (True) G2 Lane 0 Transmit Data (Complement) J1 Lane 1 Receive Data (True) [Dual-lane configurations] J2 Lane 1 Receive Data (Complement) [Dual-lane configurations] K1 Lane 1 Transmit Data (True) [Dual-lane configurations] K2 ufs 3.1 pinout